| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66553
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66583 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-495
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28185
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate |
2005-08-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2009-05-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5e09485f7c1907393b48938dc7b6d297
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_499bdc73887134be7f3461f9690b6f51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_41a78f5a6751f5f46768f06c041a8137
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8e980122b0937ebb79125f5638c94801
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_01256746433fa298de5e1db9f79f600b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_24ab2b605bce7677cea37ccc9a75caea
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8337ce723fb5641b696ac5b3ca888f87 |
| publicationDate |
2009-05-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-7531404-B2 |
| titleOfInvention |
Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer |
| abstract |
A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 Å to 60 Å. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9418853-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10043669-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011143529-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016013107-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8574990-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9761692-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8334197-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9484427-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2015295066-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9431515-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9691662-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11264479-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9406516-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9214518-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9847402-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8802524-B2 |
| priorityDate |
2005-08-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |