http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022260476-A1

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2f94790cf5bf17ef5799ba79a953aa57
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
filingDate 2022-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_45cdddb400bee50bc189d69a993bbcf7
publicationDate 2022-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber WO-2022260476-A1
titleOfInvention Power semiconductor device manufacturing method
abstract An embodiment of the present invention relates to a power semiconductor manufacturing method comprising a step of forming an active layer on a SiC substrate, wherein the step of forming an active layer can comprise: a step of spraying source gas onto the SiC substrate; a primary purging step of spraying purge gas after stopping source gas spraying; a step of spraying reactant gas after stopping primary purge spraying; and a secondary purging step of spraying purge gas after stopping reactant gas spraying. Therefore, according to embodiments of the present invention, an active layer can be formed at low temperature. Thus, a substrate or a thin film formed thereon can be prevented from being damaged by high-temperature heat. In addition, power or time for increasing the temperature of a substrate for active layer formation can be saved, and overall process time can be reduced.
priorityDate 2021-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 32.