| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0214
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02219
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02326
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02282
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate |
2013-04-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d2f3e026e9796247c65f9c234e7c79eb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0d60f8c62a539ef2d2fb8fdf07b793cc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6e25a64bca96deaef4fd0832c73006c3 |
| publicationDate |
2014-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2014306294-A1 |
| titleOfInvention |
Gap Fill Self Planarization on Post EPI |
| abstract |
The present disclosure relates to an integrated chip IC having transistors with structures separated by a flowable dielectric material, and a related method of formation. In some embodiments, an integrated chip has a semiconductor substrate and an embedded silicon germanium (SiGe) region extending as a positive relief from a location within the semiconductor substrate to a position above the semiconductor substrate. A first gate structure is located at a position that is separated from the embedded SiGe region by a first gap. A flowable dielectric material is disposed between the gate structure and the embedded SiGe region and a pre-metal dielectric (PMD) layer disposed above the flowable dielectric material. The flowable dielectric material provides for good gap fill capabilities that mitigate void formation during gap fill between the adjacent gate structures. |
| priorityDate |
2013-04-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |