| abstract |
In an embodiment, the device includes: a lower integrated circuit die having a first front side and a first rear side; An upper integrated circuit die having a second front side and a second rear side, the second rear side bonded to the first front side, the upper integrated circuit die without through-substrate vias (TSVs); A dielectric layer surrounding an upper integrated circuit die, wherein the dielectric layer is disposed on the first front side, and the dielectric layer and the lower integrated circuit die are bordered on the side; And a through via extending through the dielectric layer, wherein the through via is electrically coupled to a lower integrated circuit die, and the through via, the dielectric layer, and surfaces of the upper integrated circuit die are planar. |