| abstract |
A chip packaging structure and method, which may reduce the thickness of a package structure, increase pin density, increase the number of interconnection channels, and increase the bandwidth of a top chip. The chip packaging structure comprises: a redistribution layer (RDL) (34); a target chip (37), including an active surface and a back surface, wherein the active surface of the target chip (37) is connected with a first surface of the RDL (34); a substrate (31), a first surface of which is opposed to the back surface of the target chip (37); an interconnecting channel (33), which is located on the periphery of the target chip (37), wherein one end of the interconnecting channel (33) is connected to the first surface of the RDL (34), and the other end of the interconnecting channel (33) is connected to the first surface of the substrate (31). |