| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6bccde8faf102dc15841e2b65cb63ba0 |
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-04105
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| classificationCPCInventive |
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| classificationIPCAdditional |
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| classificationIPCInventive |
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| filingDate |
2017-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-05-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bc4b990bfac684ecd958590dc1b2fd54
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7af1ef70a33795612b5aa200421dba45
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_01a51e8eb3f29948a9957969a8d7136d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c08cc3cb37fe2236960953ce1d9200c9 |
| publicationDate |
2018-05-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9978665-B2 |
| titleOfInvention |
Semiconductor device and method of forming low profile fan-out package with vertical interconnection units |
| abstract |
A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure. A plurality of vias is formed through the insulating layer and into the first interconnect structure with the second interconnect structure disposed within the vias. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10672699-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11088079-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018138117-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10199322-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11424180-B2 |
| priorityDate |
2012-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |