| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6eb26c4eed9230e36a77fbf70757ef91
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0b364cf4ca0b781d878fe243f36e3181 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0267
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2320-0285
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0408
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2320-0223 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3677
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-20 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G5-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C19-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05B44-00 |
| filingDate |
2010-10-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2015-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_552765ab581651308599a018a8b852a5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_84693f3610bee1bc4b5809255312faa9 |
| publicationDate |
2015-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9171640-B2 |
| titleOfInvention |
Shift register and display device |
| abstract |
The shift register includes first to fourth flip-flops. A first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input to the first flip-flop. A second clock signal which is in the first voltage state in the second period and in the second voltage state in the third period and the fourth period is input to the second flip-flop. A third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input to the third flip-flop. A fourth clock signal which is in the second voltage state in the first and second periods and in the first voltage state in the fourth period is input to the fourth flip-flop. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10388222-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11575100-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021074944-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9742378-B2 |
| priorityDate |
2009-10-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |