Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0883 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-096 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0883 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-13685 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-1368 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-094 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-09407 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-09421 |
classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-094 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-096 |
filingDate |
2013-02-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2015-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_01586b738d5c3da823a8b306e0b71efa http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a5a79f4c83d6887d5708274a362a3a58 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_10941373b6a864097266d70055b7c335 |
publicationDate |
2015-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-9083334-B2 |
titleOfInvention |
Logic circuit |
abstract |
An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102 . The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10354115-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9900007-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9595964-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9444459-B2 |
priorityDate |
2008-10-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |