http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8859410-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42364 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-511 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28044 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4925 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2013-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2014-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_72c790d51683f1946b768304dd683cf1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_18bd5a8f122e2d33d662a40e667049fd http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c7eeb7c5fe0dc5a5fbafb4ecfeae8b77 |
| publicationDate | 2014-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-8859410-B2 |
| titleOfInvention | Gate stack of boron semiconductor alloy, polysilicon and high-k gate dielectric for low voltage applications |
| abstract | A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108022833-A |
| priorityDate | 2013-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 86.