| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8ff34733ee97abedbeeaac6c3951916f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3e25edbaab1e58d758d08c99debcfd36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_af77ee95399d7d5a3a244a2a3bebce86 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-76 |
| filingDate |
2009-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_654b7fb081cf4bf8c02f3e197b8feb14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_828e83f1094bf36f6c22360e060c38f7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd6e728e8b0b0a56d0ef70bc4d84fb03 |
| publicationDate |
2013-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8471307-B2 |
| titleOfInvention |
In-situ carbon doped e-SiGeCB stack for MOS transistor |
| abstract |
An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×10 19 and 2×10 20 atoms/cm 3 . The second PSD layer is Si—Ge and includes carbon at a density between 5×10 19 atoms/cm 3 and 2×10 20 atoms/cm 3 and boron at a density above 5×10 19 atoms/cm 3 . The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×10 19 atoms/cm 3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10504992-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10790133-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11251189-B2 |
| priorityDate |
2008-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |