| abstract |
In order to increase an aperture ratio, a part of or all of a gate electrode that overlaps with channel formation regions ( 213, 214 ) of a pixel TFT is caused to overlap with second wirings (source line or drain line) ( 154, 157 ). Additionally, a first interlayer insulating film ( 149 ) and a second interlayer insulating film ( 150 c ) are disposed between the gate electrode and the second wirings ( 154, 157 ) so as to decrease a parasitic capacitance. |