| abstract |
A ferroelectric non-volatile memory in which each memory cell consists of a metal-ferroelectric-metal ("MFM") capacitor and a FET on a semiconductor substrate. The MFM and the FET are separated by an interlayer dielectric layer. A local interconnect connects the gate electrode of the FET to the bottom electrode of the MFM capacitor. Preferably, the MFM is located directly above the gate electrode, and the local interconnect is a conductive plug in a filled via. Preferably, the ferroelectric thin film of the MFM comprises a layered superlattice material. Preferably, a dielectric metal oxide insulator layer is located between the gate electrode and the semiconductor substrate. |