| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
1999-08-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2000-03-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_94924591a72e5e7de23eb9a05eee622e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6fce1ab3fca8fef1cfd5f9d2a4186e05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dca7825805dde965c34d8c6c955eac93
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3169e43d184c5ab379f1ffe1f5bedde6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7a3d9de20f2662add560530d081ff233
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4cbe7d5ae8d4aee6c6f9c7155f84b929 |
| publicationDate |
2000-03-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-6040223-A |
| titleOfInvention |
Method for making improved polysilicon FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer for more reliable integrated circuits |
| abstract |
A method for making improved polysilicon FET gate electrodes having composite sidewall spacers is achieved. After forming the polysilicon gate electrodes on the substrate, a SiO 2 stress-release layer is deposited having a trapezoidal shape. A Si 3 N 4 layer is deposited and plasma etched back using the SiO 2 layer as an etch-endpoint-detect layer to form composite sidewall spacers that include portions of the trapezoidal-shaped oxide layer. The SiO 2 layer protects the source/drain areas from plasma etch damage that could cause high leakage currents. The Si 3 N 4 also extends over the SiO 2 layer at the upper edges of the polysilicon gate electrodes. This prevents erosion of the SiO 2 along the gate electrodes when the remaining oxide is removed from the source/drain areas using hydrofluoric acid wet etching. When an insulating layer is deposited over the FETs, and self-aligned contact openings are etched to the source/drain areas and extending over the gate electrodes, the Si 3 N 4 extending over the portion of the trapezoidal-shaped SiO 2 layer that forms part of the composite sidewall spacer protects the SiO 2 from etching. This results in more reliable contacts without degrading the FET performance. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005153496-A1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7785949-B2 |
| priorityDate |
1999-08-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |