| abstract |
In some embodiments, the present disclosure relates to an integrated chip (IC) having a back-side through-silicon-via (BTSV) with a direct physical connection between a metal interconnect layer and a back-side conductive bond pad. The IC has metal interconnect layers arranged within an inter-level dielectric structure disposed onto a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate, and a conductive bond pad is arranged over the dielectric layer. A BTSV extends from one of the metal interconnect layers through the substrate and the dielectric layer to the conductive bond pad. A conductive bump is arranged onto the conductive bond pad, which has a substantially planar lower surface extending from over the BTSV to below the conductive bump. Directly connecting the conductive bond pad to the BTSV reduces a size of the conductive bond thereby improving a routing capability of the conductive bond pad. |