| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b051f9f7933c758e66f6ceda5c9fb2cc |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C18-122
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C18-1245
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02219
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-208
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C18-145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C18-143
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-316
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3121
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02282
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C09D7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-314 |
| filingDate |
2009-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_39b544c2a652c7fb31185b07138aeb44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2f76a585eefed281cd9299aa2bea8d4e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_421de8a7ac25307ee1b7ecb7b512306a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_88aa9d5865bb219c9b452d82a5122325
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f73bae8d51cff769ad23a2ffee036378
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_af9424cdc57fb3e6187e5884e8211213 |
| publicationDate |
2010-01-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2010009546-A1 |
| titleOfInvention |
Aminosilanes for Shallow Trench Isolation Films |
| abstract |
The present invention is a process for spin-on deposition of a silicon dioxide-containing film under oxidative conditions for gap-filling in high aspect ratio features for shallow trench isolation used in memory and logic circuit-containing semiconductor substrates, such as silicon wafers having one or more integrated circuit structures contained thereon, comprising the steps of:n providing a semiconductor substrate having high aspect ratio features; contacting the semiconductor substrate with a liquid formulation comprising a low molecular weight aminosilane; forming a film by spreading the liquid formulation over the semiconductor substrate; heating the film at elevated temperatures under oxidative conditions.n nCompositions for this process are also set forth. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014057458-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8912353-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9640386-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9029273-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8932675-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115851004-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2013244448-A1 |
| priorityDate |
2008-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |