| abstract |
Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention. |