| abstract |
Method and structure for vertically stacking microelectronic devices are disclosed. Subsequent to appropriate deposition, patterning, trenching, and passivation subprocesses, a conductive layer is formed wherein one end comprises an external contact portion for C4 interfacing, and another end establishes electrical contact with an internal contact at the bonding interface between the two interfaced devices. The conductive layer may be formed using electroplating, and may be formed in a single electroplating treatment, to form a continuous structure from via portion to external contact portion. |