Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76849 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76856 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76832 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76856 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76849 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76879 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53295 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-532 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 |
filingDate |
2019-09-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2022-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_85137b3fde9036538c6d69a46774cbd2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e2b16337882c37b12eca7f425dd9100c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e09f58150543c6c9de8772a6219a8b57 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c12f4536862e21980d37540f7344c257 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_47a8f908465a4601af43d8a61dc85bd0 |
publicationDate |
2022-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-11335596-B2 |
titleOfInvention |
Selective deposition for integrated circuit interconnect structures |
abstract |
Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess. |
priorityDate |
2018-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |