| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5f7f120efe096284c7389702c969cf3d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-231 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-01
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B61-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-08 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311 |
| filingDate |
2017-11-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-05-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ebb223e2a8a8fde47161c74d7618babd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c4377cd553fe41711100ca562f89d4f8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_30d743e6d26609f048938183712761fb |
| publicationDate |
2019-05-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10305029-B1 |
| titleOfInvention |
Image reversal process for tight pitch pillar arrays |
| abstract |
Fabrication of a semiconductor device includes providing a semiconductor substrate, and a dielectric layer disposed over the semiconductor substrate. The dielectric layer includes a plurality of vias extending through the dielectric layer to the top surface of the semiconductor substrate. Each of the vias contains an organic planarization material. The dielectric layer is removed by plasma etching with a gas having a general chemical formula of C x H y F z wherein x is greater than 3 and y is greater than z to provide an array of pillars including the organic planarization material on the semiconductor substrate. |
| priorityDate |
2017-11-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |