| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6af9a57049d2d91c036d4f5ab49154cb |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2029-7858
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02488
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 |
| filingDate |
2015-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2016-12-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_696eaac3fb0cc12872dcccc17d871819
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d26c9f25058c05ca22dc704c6a161d52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a0f20fa33a9de771ac8956871ffdd0bb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3cced35d37ec49fa4119b17841c21def
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_efdefc64a6dbf8fe3b07312cc8c01187 |
| publicationDate |
2016-12-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9520395-B2 |
| titleOfInvention |
FinFET devices comprising a dielectric layer/CMP stop layer/hardmask/etch stop layer/gap-fill material stack |
| abstract |
Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10305029-B1 |
| priorityDate |
2014-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |