Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ca748d5cbfb6d9d2f2c6013230fccd73 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0214 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02219 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02271 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-022 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02211 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-125 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7926 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-31 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
filingDate |
2013-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2018-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bd7951732999b8dd16d43562d141922d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_444ba4bc5cbfe37362a4c38356462b91 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a9aa762a23dfebd68e66a18b20f9a8ec |
publicationDate |
2018-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
TW-I629788-B |
titleOfInvention |
Non-volatile charge trapping memory element having a deuterated layer in a multilayer charge trapping region |
abstract |
A charge trapping memory element and an article made therefrom are scaled. In one embodiment, the charge trapping memory device includes a substrate having a source region, a drain region, and a channel region electrically connected to the source and the drain. A tunneling dielectric layer is disposed over the channel region of the substrate, and a plurality of charge trapping regions are disposed on the tunneling dielectric layer. The multilayer charge trapping region includes a first deuterated layer disposed on the tunneling dielectric layer, a first nitride layer and a second nitride layer disposed on the first deuterated layer. |
priorityDate |
2012-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |