| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-3011
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-482
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 |
| filingDate |
1996-09-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
1997-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bc0e311e7cc71889f23bcafe468f3034
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cb364263362400932b60214a1ca0e35a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_17f995fa9eee2bea642e053bccafcbfc |
| publicationDate |
1997-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-311263-B |
| titleOfInvention |
Semiconductor device and method of making the same |
| abstract |
A semiconductor device contains: 1) wiring layer on the main surface of the substrate; 2) the first isolation layer located on the wiring layer with holes to the main surface of the substrate; 3) the second isolation layer formed on the first isolation layer with holes to the first isolation layer and having larger etching selection ratio as compared to the first isolation layer; 4) side wall spacer formed inside of the holes on the second isolation layer;5) conducting layer formed inside of the holes on the first and the second layer which is conducted to the substrate but isolated from the wiring layer. |
| priorityDate |
1996-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |