| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-04953
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-04941 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53209
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02263
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76856
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76858
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53252
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76846
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-288 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2020-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0de49a93fe27af1f750c2aa3752bd7d5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_21dba2e44631d6e2727a0484d6302d68 |
| publicationDate |
2021-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-202109748-A |
| titleOfInvention |
Low resistivity interconnects for integrated circuit and methods of forming the same |
| abstract |
The present disclosure provides an interconnect for an integrated circuit and a method of forming the same. The method of forming an interconnect for an integrated circuit includes: identifying an interconnect barrier material, identifying a plurality of potential dopant elements, creating an ensemble of potential barrier structures including the interconnect barrier material doped at a plurality of doping positions and a plurality of doping amounts for each of the plurality of potential dopant elements, calculating a density of states for each of the barrier structures of the ensemble, selecting a dopant element and a doping amount based on the density of states, and depositing a barrier layer including an alloy, the alloy including the interconnect barrier material and the selected dopant element at the selected doping amount. The interconnect of the present disclosure may decrease the resistivity of the conductive metal/barrier interface and the vertical resistivity of the conductive metal/barrier stack. |
| priorityDate |
2019-01-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |