| abstract |
A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip, which has an active surface and a rear surface, where the first chip is mounted on the chip placement area by its rear surface, and a plurality of first pads are disposed on the active surface each with a first bump formed thereupon; a plurality of metal wires, which electrically connect the first bumps to the contacts; a second chip, which has an active surface and a rear surface, where a plurality of second pads are disposed on the active surface of the second chip each with a second bump formed thereupon, and the second chip is mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively; an encapsulant, which is used to cover the substrate, the first chip, the second chip, and the metal wires. |