| Predicate |
Object |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4983
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate |
2002-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2004-07-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20040068311-A |
| titleOfInvention |
Composite spacer liner for improved transistor performance |
| abstract |
The complex oxide / nitride liners 24 and 25 are formed under the gate electrode sidewall spacer 40 to fabricate a semiconductor device having improved transistor performance. Specifically, conformal oxide liner 24 is deposited by decoupled plasma deposition, conformal nitride liner 25 is deposited by decoupled plasma deposition, and sidewall spacers 40 are deposited and then etched. . |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101274960-B1 |
| priorityDate |
2001-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |