| abstract |
A method and package structure for packaging a wafer level system, the method comprising: providing a device wafer comprising a first front surface on which a plurality of first chips are integrated and a first back surface opposite the first front surface; providing a plurality of second chips; forming an adhesive layer on the first front surface; patterning the adhesive layer, and forming a plurality of first via holes through which the first front surface is exposed in the adhesive layer; installing a second chip on the remaining adhesive layer so as to correspond one-to-one with the first via hole and cover an uppermost portion of the first via hole so that the device wafer and the second chip are bonded; etching the first back surface and forming in the device wafer a first via hole and a second via hole passing through each other, the second via hole and the first via hole forming a first conductive via hole; and forming a first conductive pillar electrically connected to the second chip in the first conductive via hole. The present invention improves the electrical connection performance of the first conductive pillar by first forming a first via hole and then forming a second via hole, thereby preventing the problem that the first via hole opening size is larger than the second via hole opening size . |