| abstract |
The present invention relates to a wafer-level chip-scale package of a power semiconductor, by attaching a power semiconductor having a dual N-channel directly to a lead frame to drop contact resistance, and a low-resistance common drain electrode crossing two semiconductor devices. is formed thick to lower the resistance in the entire current path. Therefore, a wafer-level chip-scale package of a power semiconductor with low switching loss can be manufactured. In addition, by selectively manufacturing a wafer-level chip-scale package of the power semiconductor by using the back side grinding, there is an effect of minimizing the damage of the power semiconductor during wafer handling by removing the warpage of the wafer. |