http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100485162-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66772 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78648 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-0392 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2003-08-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2005-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2005-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100485162-B1 |
| titleOfInvention | MOS transistor and fabrication method thereof |
| abstract | The present invention relates to a MOS transistor and a method of manufacturing the same, and an object thereof is to provide a MOS transistor having a novel structure that is advantageous for miniaturization and a method of manufacturing the same. To this end, the present invention comprises the steps of forming a drain having a predetermined thickness by implanting impurities into the upper surface of the semiconductor substrate is formed trenches to isolate the device active region; Selectively etching the drain and the semiconductor substrate so as to protrude the semiconductor substrate under the drain and the drain having a predetermined width on both sidewalls of the trench; Forming sidewalls on both sidewalls of the protruding semiconductor substrate below the drain, and forming a protective film on the semiconductor substrate and the drain except the sidewalls, and then removing the sidewalls; Isotropically etching the semiconductor substrate exposed by removing the sidewalls using the passivation layer as a mask to form gate holes, and forming vertical channels having a width narrower than the drain on both sidewalls of the trench below the drain; Removing the passivation layer and forming a gate oxide layer on the drain, the vertical channel and the upper surface of the semiconductor substrate; Implanting impurities into a semiconductor substrate below the vertical channel to form a source; Forming a gate in the gate sphere to manufacture a MOS transistor. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8022457-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8283714-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8482045-B2 |
| priorityDate | 2003-08-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.