http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100442885-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31604 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3185 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31616 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-518 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28194 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28202 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42368 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-318 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2002-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2004-08-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2004-08-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100442885-B1 |
| titleOfInvention | Method for manufacturing multi-thickness gate dielectric layer of semiconductor device |
| abstract | A method of manufacturing a multi-thickness gate dielectric layer of a semiconductor device is provided. In a method of manufacturing a gate dielectric layer according to an aspect of the present invention, a first dielectric layer is formed on a semiconductor substrate, a second dielectric layer is formed of a dielectric material different from the dielectric material constituting the first dielectric layer on the first dielectric layer, and the second A portion of the second dielectric layer is selectively removed so that the portion of the first dielectric layer under the dielectric layer is selectively exposed. After selectively removing a portion of the exposed first dielectric layer portion to selectively expose the semiconductor substrate portion below the exposed first dielectric layer portion, a third dielectric layer having a thickness smaller than the thickness of the first dielectric layer is applied to the exposed semiconductor substrate portion. Form. Accordingly, the gate includes a relatively thick portion composed of the first dielectric layer and the remaining second dielectric layer portion, a relatively intermediate portion composed of the remaining first dielectric layer portion, and a relatively thin portion composed of the third dielectric layer. A dielectric layer is formed. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9786761-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100957873-B1 |
| priorityDate | 2002-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 42.