http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-5670603-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28114 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31051 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28525 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42364 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40114 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1037 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-308 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3213 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-41 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2013-04-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2015-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2015-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-5670603-B1 |
| titleOfInvention | Semiconductor device manufacturing method and semiconductor device |
| abstract | It is an object of the present invention to provide an SGT manufacturing method which is a gate last process and an SGT having a structure in which an upper part of a columnar semiconductor layer functions as an n-type semiconductor layer or a p-type semiconductor layer by a work function difference between a metal and a semiconductor. . Forming a first insulating film around the fin-shaped semiconductor layer; forming a columnar semiconductor layer on the fin-shaped semiconductor layer; creating a second insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; A polysilicon gate electrode covers the second insulating film, forms a diffusion layer above the fin-like semiconductor layer and below the columnar silicon layer, and a compound of a metal and a semiconductor above the diffusion layer above the fin-like semiconductor layer Forming an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and depositing a first metal; A gate electrode and a metal gate wiring are formed, a sidewall made of a third metal is formed on the upper side wall of the columnar semiconductor layer, and a support made of the third metal is formed. Doworu and the pillar-shaped semiconductor layer top surface is to solve the aforementioned problems by, characterized in that it is connected. |
| priorityDate | 2013-04-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.