| abstract |
A semiconductor device with reduced parasitic capacitance is provided. A first insulating layer, a first oxide layer on the first insulating layer, a semiconductor layer on the first oxide layer, a source electrode layer and a drain electrode layer on the semiconductor layer, and , A second insulating layer on the first insulating layer, a third insulating layer on the second insulating layer, the source electrode layer, and the drain electrode layer, a second oxide on the semiconductor layer, A gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; a third insulating layer; a second oxide layer; a gate insulating layer; and a fourth over the gate electrode layer. And the second insulating layer has a region in contact with the first oxide layer, the semiconductor layer, the source electrode layer, and the drain electrode layer on the side surface, and the upper surface of the second insulating layer is , The source electrode layer, and the drain electrode layer, and the second oxide layer includes the first oxide layer, the source electrode layer, and the drain electrode layer. In the electrode layer, the second insulating layer, and a semiconductor device having a side surface in contact with the region of the third insulating layer. [Selection] Figure 1 |