| abstract |
(57) [Summary] [PROBLEMS] To achieve miniaturization of interlayer vias and wiring patterns and a reduction in overall thickness, shorten the wiring length of a semiconductor chip, and achieve high-speed processing and improvement in reliability. SOLUTION: A first exposure process and a second exposure process in which unit wiring layers 8 to 12 have different exposure amounts in portions corresponding to vias 13 and a circuit pattern 25 of an insulating layer 24 made of a photosensitive insulating material. Forming a conductor layer 28 over the entire surface after performing a two-step exposure treatment of the above and a development treatment for removing the exposed portion, and polishing the conductor layer 28 until the insulating layer 24 is exposed to flatten the surface. Thereby, fine and high-density vias 13 and circuit patterns 25 are formed in the insulating layer 24. |