http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1138058-A2
Outgoing Links
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|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b7317808024e524eea40a6c5a5ad6a22 |
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| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66583 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4983 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-43 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate | 2000-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4854603e0bb828d8473767e418dbd475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_211f38ca26d8c582b3e4804692eb292e |
| publicationDate | 2001-10-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-1138058-A2 |
| titleOfInvention | Method of manufacturing a variable work function gate mosfet using a dummy gate |
| abstract | In a method of manufacturing a semiconductor device comprising a transistor having a gate (22) insulated from a channel (13) by a gate dielectric (17), which channel (13) is provided in an active region (4) of a first conductivity type provided at a surface (2) of a semiconductor body (1) and has a length L over which it extends between a source zone (11,9) and a drain zone (12,9) of a second conductivity type, the active region (4) of the first conductivity type is defined in the semiconductor body (1), and a dielectric layer (14) is applied which is provided with a recess at the area of the gate (22) planned to be provided at a later stage, in which recess an insulating layer is applied, forming the gate dielectric (17) of the transistor. Then, a first conductive layer and a second conductive layer are applied, the first conductive layer being relatively thin compared to the width of the recess, which first conductive layer and second conductive layer jointly form the gate (22) of the transistor and fill the recess in the dielectric layer (14). The gate comprises a central portion (21) and side end portions (19) positioned along either side of the central portion (21), which central portion (21) and side end portions (19) are in contact with the gate dielectric (17) and jointly establish a work function of the gate (22) varying across the length L of the channel (13). |
| priorityDate | 1999-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 46.