| abstract |
A method is given for planarizing an integrated circuit structure just prior to the formation of metallurgy interconnection lines on the integrated circuit. The method begins with the integrated circuit intermediate product having device elements (14, 16, 20) formed therein but before interconnection metallurgy (42, 44, 46) has been formed on the principal surface of the product. A glass layer (40) is deposited in a non-conformal way onto the principal surface of the integrated circuit. The glass is chosen to have a thermal coefficient of expansion that approximates that of silicon and has a softening temperature of less than about 1200°C. The structure is heated to cause the flow of glass (40) on the surface of the integrated circuit product to fill in the irregularities therein and to thereby planarize the integrated circuit surface. Openings are then formed through the glass (40) down to the device elements (14, 16, 20) of the integrated circuit. The interconnection metallurgy (42,44,46) is formed over the surface of glass (40) and through the openings of the glass to interconnect the device elements (14, 16, 20) of the integrated circuit. The glass (40) may be deposited by various methods which include the sedimentation methods of spraying, centrifuging and spin-on plus sputtering or evaporation methods. |