http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102012200236-B3
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fd446fb0d73aa96d044fea2eaa3c8ebc |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1608 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66068 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30655 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate | 2012-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2013-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c0e56aac80415e7d70c731e9cbf8f6d3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e0125c0162e0debf31cc492bbe46e13a |
| publicationDate | 2013-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102012200236-B3 |
| titleOfInvention | Process for structuring silicon carbide and SiC trench MOSFET |
| abstract | The present invention provides a method of patterning silicon carbide and a SiC trench MOSFET. The method comprises the steps of: forming a masking layer (5) having a mask opening (5a) corresponding to a trench region to be formed on a SiC substrate (1); Performing an anisotropic plasma etching step (E1), wherein a first trench region (G) is formed in the SiC substrate (1); Performing a passivation step (P1), wherein at a trench bottom (B) of the first trench region (G) and at an upper side (O) of the masking layer (5) a passivation layer (10) having a first layer thickness (d1) is formed and wherein at one Trench sidewall (S) and on an inside (I) of the masking layer (5) in the mask opening (5a) the passivation layer (10) is formed with a second layer thickness (d2) which is greater than the first layer thickness (d1); and re-performing the anisotropic plasma etching step (E2), wherein the passivation layer (10) is removed from the trench bottom (B) of the first trench region (G) and the top surface (O) of the masking layer (5) and attached to the trench sidewall (S ) and on the inner side (I) of the masking layer (5) in the mask opening (5a) is at least partially preserved, and wherein a second enlarged trench region (G ') is formed in the SiC substrate (1). |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111081547-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111081547-B |
| priorityDate | 2012-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 43.