| abstract |
The present application provides gate oxides with increased corner thicknesses for nanostructured transistors. A device includes a semiconductor nanostructure and an oxide layer, the oxide layer including horizontal portions on top and bottom surfaces of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and The corner part on the corner. The horizontal portion has a first thickness. The vertical portion has a second thickness. The corner portion has a third thickness. Both the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. The gate electrode surrounds the high-k dielectric layer. |