| abstract |
The stacked package of the embodiment may include: an upper chip over the lower chip; a backside passivation layer covering the backside surface of the lower chip and having a thickness substantially equal to the height of the protrusion of the lower via electrode; and a backside bump , substantially in contact with the protrusions; and front-side bumps, electrically coupled to the chip contacts of the upper chip, and physically and electrically connected to the backside bumps. The backside passivation layer may include a first insulating layer provided over the sidewalls of the protrusion and over the backside surface of the lower chip. Embodiments of methods of manufacture are also disclosed. |