| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fb81149bf5661924f33b97120cf99bf8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_48d9b5b5c83f8d82d1080f2118962043
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_59637b35e4eaff22d062490678396043
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ebf50bcbdb2c051d45cf6383f9bae116 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-033 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G03F7-167
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G03F7-0757
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76838 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G03F7-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G03F7-075
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302 |
| filingDate |
1999-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ff836032f5efe7904e01e2069faaa7eb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_76654da858785a84cf0ed5472b523dff
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9295a8e0d2b976e5e62534621359ac19
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a3db9e2099ee562d9c9619e8e3de2e07 |
| publicationDate |
1999-09-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-9944232-A1 |
| titleOfInvention |
Method of increasing alignment tolerances for interconnect structures |
| abstract |
Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-10133873-B4
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-10133873-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7265405-B2 |
| priorityDate |
1998-02-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |