http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022233734-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_37b40dff22cc7eb6404edfa0c25f7430 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-86 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0676 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate | 2022-04-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f92080aea8b7b11dd725b071a5047f19 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_78720cacd7bcb16a7e459b913ce0c755 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6dd0c8c80a39cac21873adca21bd8cbb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8cbdb6133a3b7372592b34497433c0e0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a41859466cb1780d440b09c3f80e4919 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0fe52c198da78ff6fdb314fc5c6db32b |
| publicationDate | 2022-11-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2022233734-A1 |
| titleOfInvention | Semiconductor structure forming a plurality of transistors |
| abstract | A semiconductor structure forming a plurality of transistors is disclosed. The semiconductor structure comprising: a source layer (110); a plurality of vertical nanowires (140) erecting from the source layer (110); a first spacer layer arranged on the source layer (110) and around each of the plurality of vertical nanowires (140); a gate layer (120) arranged on the first spacer layer and around each of the plurality of vertical nanowires (140); a second spacer layer arranged on the gate layer (120) and around each of the plurality of vertical nanowires (140); and a drain layer (130) arranged on the second spacer layer and in contact with each of the plurality of vertical nanowires (140); wherein the gate layer (120) comprises a first gate (121) and a second gate (125) each comprising a plurality of gate fingers (122, 126), wherein the first gate (121) comprises a first interconnecting gate portion (123) interconnecting the gate fingers (122) of the first gate (121), wherein the second gate (125) comprises a second interconnecting gate portion (127) interconnecting the gate fingers (126) of the second gate (125), wherein the plurality of gate fingers (122) of the first gate (121) is interleaved with the plurality of gate fingers (126) of the second gate (122), wherein the first gate (121) is a gate of a first transistor (101) and the second gate (125) is a gate of a second transistor (105). |
| priorityDate | 2021-05-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.