| abstract |
Disclosed are a parallel structure and a manufacturing method therefor, and an electronic device comprising the parallel structure. The parallel structure comprises source/drain layers and channel layers alternately stacked on a substrate and a gate stack formed around at least part of the periphery of each channel layer. Each channel layer, the source/drain layers at the upper and lower sides thereof, and the gate stack formed around the channel layer form corresponding semiconductor devices. In each semiconductor device, one of the source/drain layers at the upper and lower sides of the corresponding channel layer is in contact with a first conductive channel provided at the periphery of an active region, the other one of the source/drain layers is in contact with a second conductive channel provided at the periphery of the active region, and the gate stack formed around the channel layer is in contact with a third conductive channel provided at the periphery of the active region. The first conductive channel is common for all the semiconductor devices, the second conductive channel is common for all the semiconductor devices, and the third conductive channel is common for all the semiconductor devices. |