| abstract |
A semiconductor device, comprising an insulated gate field effect transistor (1) connected in series with a field effect transistor(2), FET,wherein the FET (2) comprises several parallel conductive layers(n1-n5, p1-p4), and wherein a substrate (11) of first conductivity type is arranged as the basis for the semiconductor device, stretching under both transistors (1, 2), a first layer of a second conductivity type (n1)is arranged stretching over the substrate (11), wherein on top of this first layer (n1) are arranged several conductive layers with channels formed by several of the first conductivity type doped epitaxial layers (n2-n4) with layers of a first conductivity type (p1-p4) on both sides, wherein the uppermost layer (n5)of the device being substantially thicker than the directly underlying several parallel conductive layers(p1-p4, n1-n4), and that the field effect transistor (2), JFET, is isolated with deep poly trenches of first conductivity type, DPPT, (22) on the source side of the JFET, and the insulated gate field effect transistor (1) is isolated with deep poly trenches of the first conductivity type, DPPT, (22, 23) on both sides, and a further isolated region (5) comprising logics and analogue control functions is isolated with deep poly trenches of the first conductivity type, DPPT, (23, 24) on both sides. |