| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b6caea61bfde8a45e01a8deabff80d97 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-823 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-845
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L45-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-24 |
| filingDate |
2018-05-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4e18623efaf70d27d754c6248dbd8fdf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5b40e71cd343554df1888eec5a92011b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_28a15703cd1556cbee485a35ddcd0103
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c4a5e937066d2ce042b84dd7e40756c2 |
| publicationDate |
2019-02-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2019032166-A1 |
| titleOfInvention |
TWO-DIMENSIONAL NETWORK OF CIRCULAR GRID VERTICAL FIELD EFFECT TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME |
| abstract |
A two-dimensional array of vertical field effect transistors (200A) comprising a one-dimensional array of ladder-shaped gate electrode lines (52), each comprising a pair of rail portions (522) which are extend laterally along a first horizontal direction (hd1) and which are spaced along a second horizontal direction (hd2), and step portions (524) extending between the rail portions along the second horizontal direction. Each vertical field effect transistor comprises a gate dielectric (50) located in an opening defined by a neighboring pair of step portions, and a vertical semiconductor channel (14) laterally surrounded by the gate dielectric. The two-dimensional array of vertical field effect transistors can be used to select vertical bit lines (90) of a three-dimensional ReRAM device (300). |
| priorityDate |
2017-08-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |