| abstract |
A method for device layout (10) with vertical transistors includes identifying active area regions (18, 28) in a layout (10) of a semiconductor device with vertical transistors. Sets of adjacent active area regions (18, 28) having a same electrical potential are determined. The sets of adjacent active area regions (18, 28) to be merged are prioritized based upon one or more performance criterion. The sets of adjacent active area regions (18, 28) are merged to form larger active area regions according to a priority． |