http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2018008609-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_60e66be87630d7cef0ce770e1d898eec http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d68354266fb6a02eae0b85e7585a8e07 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-30 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11587 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1159 |
| filingDate | 2017-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_be4412b2c1b437b3b22367777869709c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ab229bf1cc40fb445dba3cb788381356 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fecd16fded7acd27306c83de890d64d2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fe9ecf8f8833ccf05f21f367265706d3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_123237da0f8ef9fbf30f786c086b005b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_53488dd71d53c11055a45e401c0b14fc |
| publicationDate | 2018-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2018008609-A1 |
| titleOfInvention | Semiconductor storage element, other elements, and method for manufacturing same |
| abstract | Provided are a semiconductor storage element in which a storage member having a high-aspect shape with a width of not more than 100 nm and a height of twice or more of the width, and a method for manufacturing the same.nThe semiconductor storage element comprises a stacked structure in which a storage member 2 and a conductor 3 are superposed on a semiconductor substrate 1, and is characterized in that: the storage member 2 has a bottom surface 12 in contact with the semiconductor substrate 1; the storage member 2 has an upper surface 10 in contact with the conductor 3; the storage member 2 has side surfaces 11 which are in contact with and surrounded by a dividing wall 4; the bottom surface 12 of the storage member 2 has a width of not more than 100 nm; the shortest distance between the conductor 3 and the semiconductor substrate 1 is twice or more of the width of the bottom surface 12 of the storage member 2; the side surface 11 of the storage member 2 has a width which is either the same as the width of the bottom surface 12 and constant at any position above the bottom surface 12, or the widest at a position other than the bottom surface 12 and above the bottom surface 12. |
| priorityDate | 2016-07-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.