| abstract |
A semiconductor device comprises a first source/drain region (802) arranged on a semiconductor substrate (102), a second source/drain region (1002) arranged on the semiconductor substrate (102), a bottom spacer (1602) arranged on the first source/drain region (802), and a bottom spacer (1602) arranged on the second source/drain region (1002). A first gate stack (2602a) having a first length (L1) is arranged on the first source/drain region (802). A second gate stack (2602b) having a second length (L2) is arranged on the second source/drain region (1002), the first length (L1) is shorter than the second length (L2). A top spacer (2702) is arranged on the first gate stack (2602a), and a top spacer (2702) is arranged on the second gate stack (2702b). |