| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_962adbf7d50e742218f3d536a63df612 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C09J201-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-4828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C09J11-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C09J11-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C09J7-10 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C09J11-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C09J201-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C09J7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-301
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C09J11-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-065 |
| filingDate |
2017-02-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fec481b7ef98c74252d2e171cd5252c8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ffbb78d41aa77e44c5824c866b672933 |
| publicationDate |
2017-10-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2017175480-A1 |
| titleOfInvention |
Sheet for producing three-dimensional integrated laminated circuit and method for producing three-dimensional integrated laminated circuit |
| abstract |
This sheet 1 for producing a three-dimensional integrated laminated circuit, which is interposed between a plurality of semiconductor chips having through-electrodes and is used to adhere the semiconductor chips to each other and obtain a three-dimensional integrated laminated circuit, is provided with at least a curable adhesive layer 13, wherein the material that constitutes the adhesive layer 13 has a pre-curing melt viscosity at 90 °C of 1.0×10 0 -5.0×10 5 Pa·s, and the cured product has an average linear expansion coefficient at 0-130 °C of 45 ppm or less. This sheet 1 for producing a three-dimensional integrated laminated circuit can be used to produce a three-dimensional integrated laminated circuit in which connection resistance between the semiconductor chips does not easily change and which is highly reliable. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111712946-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111684623-A |
| priorityDate |
2016-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |