| abstract |
The present invention provides a three-dimensional integrated circuit laminate filled with an interlayer filler composition having both high thermal conductivity and low linear expansion. A semiconductor substrate laminate 1 in which at least two semiconductor substrates 10, 20, 30 on which semiconductor device layers 11, 21, 31 are formed is laminated, and a resin is interposed between the semiconductor substrates 10, 20, 30. A three-dimensional integrated circuit laminate including first interlayer filler layers 40 and 50 containing (A) and an inorganic filler (B) and having a linear expansion coefficient of 5 ppm to 70 ppm. [Selection] Figure 1 |