| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ee22da9644434dbe1120d1c74efeb947
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b51d6abd3a23240562d3049c674beada |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76865
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76846
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-535
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate |
2013-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_129d727076d31f5ec2b36f05cdab7b1a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_085bf9b5d73f40e989c9c1ad6e58f56d |
| publicationDate |
2015-05-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2015076792-A1 |
| titleOfInvention |
Microelectronic transistor contacts and methods of fabricating the same |
| abstract |
A transistor contact of the present description may be fabricated by forming a via through an interlayer dielectric layer disposed on a microelectronic substrate, wherein the via extends from a first surface of the interlayer dielectric layer to the microelectronic substrate forming a via sidewall and exposing a portion of the microelectronic substrate. A conformal contact material layer may then be formed adjacent the exposed portion of the microelectronic substrate, the at least one via sidewall, and the interlayer dielectric first surface. An etch block plug formed within the via proximate the microelectronic substrate. The contact material layer not protected by the etch block plug may be removed followed by the removal of the etch block plug and the filling the via with a conductive material. |
| priorityDate |
2013-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |