http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2007037823-A1

Outgoing Links

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filingDate 2006-08-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_215a8faf6380a2ab86d67b7a05342a91
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publicationDate 2007-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber WO-2007037823-A1
titleOfInvention Non-volatile programmable memory cell for programmable logic array
abstract A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor (22) of a first conductivity type in series with a volatile MOS transistor (24) of a second conductivity type. The non-volatile MOS transistor (22) may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor or a nano-crystal transistor. A volatile MOS transistor (24), an inverter or a buffer (20) may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor (22) and the volatile MOS transistor (22).
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011511440-A
priorityDate 2005-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 24.