| abstract |
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer [216] is formed on the semiconductor substrate. A channel dielectric layer [208,208'] on the device dielectric layer [216] has an opening formed therein. A barrier layer [226,226'] lines the channel opening. A conductor core [230,230'] fills the opening over the barrier layer [226,226']. By using a polishing solution [252,252'] having a high selectivity from the conductor core [230,230'] to the barrier layer [226,226'] in conjunction with a polish pad, a very thin barrier layer [226,226'] may be used without the conductor core [230,230'] and dielectric layer [208,208'] being subject to erosion and the conductor core [230,230'] being subject to dishing. |